It is well known that in transferring a digital signal a buffer memory is used to exchange data between two digital signal processing systems in order to absorb fluctuation of a clock caused by the difference in clock speed between a self-station and the other station, a change in temperature on a transmission line, etc.
FIG. 1 illustrates the structure of a conventional memory device which performs the above-described process.
In FIG. 1, a data signal, input to an input terminal 300, is sent to a buffer memory circuit 306, while a first clock is sent to a write address counter circuit 303.
The write address counter circuit 303 counts the first clock, and outputs a write clock and a write address signal to write the input data signal.
The write clock and write address signal are supplied respectively to the write clock input terminal and write address signal input terminal of the buffer memory circuit 306. Based on these signals, the input data signal is stored at a designated address in the buffer memory circuit 306.
A second clock is sent to a read address counter circuit 313. The read address counter circuit 313 counts the second clock, and outputs a read clock and a read address signal.
The read clock and read address signal are respectively sent to the read clock input terminal and read address signal input terminal of the buffer memory circuit 306.
Based on these signals, the input data signal being stored at the designated address in the buffer memory circuit 306 is read out and sent to an output terminal 316.
The write address signal and the read address signal are supplied to a phase comparator 307, which provides a phase comparison signal corresponding to a phase difference between those address signals. The phase comparison signal, which shows the difference between the data writing speed and the data reading speed of the buffer memory 306, is acquired from a differential signal between the write address signal and the read address signal. The phase comparison signal is sent to a signal processor 311.
Based on the phase comparison signal, the signal processor 311 outputs a signal for slowing a read clock cycle when the second clock cycle is faster than the first clock cycle. When the second clock cycle is slower, the signal processor 311 outputs a signal for quickening the read clock cycle. The output signal of the signal processor 311 is sent as a read address counter control signal to the control terminal of the read address counter circuit.
The operation of the circuit shown in FIG. 1 will now be explained referring to FIG. 2.
In FIG. 2, (a) shows a write clock, (b) a write address signal, (c), (e) and (g) read clocks, and (d), (f) and (h) read address signals.
When the cycles of the first and second clocks are equal to each other, the number of pieces of input data in one frame has only to be equal to that of output data in one frame. Thus, stuffing bits 410 corresponding to stuffing bits 409 (previously inserted) in the write clock has only to be inserted (see FIG. 2 (c) and (d)).
If the second clock cycle is slower than the first clock cycle, the number of pieces of data to be written into the buffer memory circuit 306 is larger than that of data to be read out from the buffer memory circuit 306. Accordingly, the buffer memory circuit 306 overflows. It is therefore necessary to read out extra data at the position of the stuffing bits 410 in the read clock (c) once in some frames (see FIG. 2 (e) and (f)).
If the second clock cycle is faster than the first clock cycle, the number of pieces of data to be written into the buffer memory circuit 306 is less than that of data to be read out from the buffer memory circuit 306, thus causing the buffer memory circuit 306 to become a memory-slipping state. It is therefore necessary to add stuffing bits 412 at the position of the stuffing bits 410 in the read clock (c) once in some frames so as to perform empty data reading (see FIGS. 2 (g) and (h)).
Through above-described operation, it is possible to cope with the case where the first and second clocks have different cycles.
If the first and second clocks are asynchronous signals, or if both clocks, though synchronous signals, have a relative phase fluctuation, the phases of signals output from the write address counter circuit 303 and the read address counter circuit 313 are also shifted. A spike therefore occurs in the phase comparison signal acquired through phase comparison on those output signals.
When the phase comparison signal is sent directly to the read address counter circuit 313, the spike of the phase comparison signal ma match with the edge of the second clock. In this case, the read address counter circuit 313 will not be properly controlled to have a synchronism, causing a memory slip by which the read address passes the write address.
The prior art is therefore provided with the signal processor 311 to process the phase comparison signal. In other words, after smoothing the spike of the phase comparison signal by means of a capacitor or the like to eliminate the spike, the signal processor 311 in FIG. 1 detects a phase-shifted direction or the like and sends it as a read address counter control signal to the read address counter circuit 313.
As described above, the conventional memory device uses an analog processor as a signal processor. The conventional memory device therefore needs adjusting steps for determining whether or not the write address and the read address have the proper phase difference, has a difficulty in achieving circuit integration with a digital circuit, and is not stable to an aged deterioration.
It is therefore an object of the present invention to provide a stable memory device which is designed entirely into a digital circuit and has no aged deterioration.